The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to a technique for chemical mechanical polishing silicon.
An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. After each layer is deposited, it may be etched to create circuitry features. One fabrication step involves the formation of vias, plugs and lines to provide conductive paths between thin film circuits. Vias can be created by depositing a conductive layer, such as polycrystalline silicon (polysilicon or p-Si), over a patterned insulative layer, and then planarizing the polysilicon layer by polishing or etching until the insulative layer is exposed. The portions of the polysilicon layer remaining between the raised pattern of the insulative layer form the vias, plugs and lines.
Chemical mechanical polishing (CMP) is one accepted method of planarizing and exposing the insulative layer. This method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a moving, e.g., rotating, polishing pad. The polishing pad may be either a "standard" pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, or a chemical solution without abrasive particles if a fixed abrasive pad is used, is supplied to the surface of the polishing pad. An effective CMP process not only provides a high polishing rate, but also provides a substrate surface which is finished (lacks small-scale roughness) and flat (lacks large-scale topography). In addition, an effective CMP process produces minimal dishing (over-polishing of the polysilicon layer so that it is lower than the insulative layer) and erosion (removal of the insulative layer).
One problem that has been encountered in CMP, particularly in the polishing of polysilicon layers, is non-uniform polishing, such as the so-called "center slow effect", which is the tendency for the substrate center to be polished more slowly than the substrate edge. The center slow effect typically results in underpolishing (the removal of too little material) at the central portion of the substrate. Equivalently, if the polishing parameters are changed to increase the amount of material removed from the substrate central portion, then the outer portion of the substrate will be overpolished, resulting in dishing and erosion. The underpolishing of the substrate center or the overpolishing of the substrate edge reduces the overall flatness of the substrate, making either the center or the edge of the substrate unsuitable for integrated circuit fabrication and reducing process yield.